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Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U)
3-131 Instruction SetSPRU733
Load Halfword From Memory With a 5-Bit Unsigned Constant Offset
or Register Offset
LDH(U)
Syntax Register Offset
LDH (.unit) *+baseR[offsetR], dst
or
LDHU (.unit) *+baseR[offsetR], dst
Unsigned Constant Offset
LDH (.unit) *+baseR[ucst5], dst
or
LDHU (.unit) *+baseR[ucst5], dst
.unit = .D1 or .D2
Compatibility C62x, C64x, C67x, and C67x+ CPU
Opcode
31 29 28 27 23 22 18 17 13 12 9 8 7 6 4 3 2 1 0
creg z dst baseR offsetR/ucst5 mode 0 y op 0 1 s p
3 1 5 5 5 4 1 3 1 1
Description Loads a halfword from memory to a general-purpose register (dst). Table 3−19
summarizes the data types supported by halfword loads. Table 3−11
(page 3-33) describes the addressing generator options. The memory
address is formed from a base address register (baseR) and an optional offset
that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). If an offset
is not given, the assembler assigns an offset of zero.
offsetR and baseR must be in the same register file and on the same side as
the .D unit used. The y bit in the opcode determines the .D unit and register
file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register
file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register
file.
offsetR/ucst5 is scaled by a left-shift of 1 bit. After scaling, offsetR/ucst5 is
added to or subtracted from baseR. For the preincrement, predecrement,
positive offset, and negative offset address generator options, the result of the
calculation is the address to be accessed in memory. For postincrement or
postdecrement addressing, the value of baseR before the addition or subtrac-
tion is the address to be accessed in memory.
Table 3−19. Data Types Supported by LDH(U) Instruction
Mnemonic
op
Field
Load Data Type SIze
Left Shift of
Offset
LDH 1 0 0 Load halfword 16 1 bit
LDHU 0 0 0 Load halfword unsigned 16 1 bit