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Interrupt Detection and Processing
Interrupts5-18 SPRU733
5.4.3 Actions Taken During Nonreset Interrupt Processing
During CPU cycles 6 through 14 of Figure 5−4, the following interrupt proces-
sing actions occur:
Processing of subsequent nonreset interrupts is disabled.
For all interrupts except NMI, the PGIE bit is set to the value of the GIE bit
and then the GIE bit is cleared.
For NMI, the NMIE bit is cleared.
The next execute packets (from n + 5 on) are annulled. If an execute
packet is annulled during a particular pipeline stage, it does not modify any
CPU state. Annulling also forces an instruction to be annulled in future
pipeline stages.
The address of the first annulled execute packet (n + 5) is loaded in NRP
(in the case of NMI) or IRP (for all other interrupts).
During cycle 7, IACK is asserted and the proper INUMn signals are
asserted to indicate which interrupt is being processed. The timings for
these signals in Figure 5−4 represent only the signals’ characteristics
inside the CPU. The external signals may be delayed and be longer in
duration to handle external devices. Check the device-specific
data manual for your timing values.
IFm is cleared during cycle 8.
A branch to the address held in ISTP (the pointer to the ISFP for INTm)
is forced into the E1 phase of the pipeline during cycle 9.