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RSQRDP Double-Precision Floating-Point Square-Root Reciprocal Approximation
3-202 Instruction Set SPRU733
Notes:
1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits
are set.
2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set.
3) If src2 is a negative, nonzero, nondenormalized number, NaN_out is
placed in dst and the INVAL bit is set.
4) If src2 is a signed denormalized number, signed infinity is placed in dst
and the DIV0, INEX, and DEN2 bits are set.
5) If src2 is signed 0, signed infinity is placed in dst and the DIV0 and INFO
bits are set. The Newton-Rhapson approximation cannot be used to
calculate the square root of 0 because infinity multiplied by 0 is invalid.
6) If src2 is positive infinity, positive 0 is placed in dst.
Pipeline
Stage
E1 E2
Read src2_l
src2_h
Written dst_l dst_h
Unit in use
.S
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP,
CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be
reduced by one, because these instructions read the lower word of the DP
source one cycle before the upper word of the DP source.
Instruction Type 2-cycle DP
Delay Slots 1
Functional Unit
Latency
1
See Also RCPDP, RSQRSP
Example
RCPDP .S1 A1:A0,A3:A2
Before instruction 2 cycles after instruction
A1:A0
4010 0000h 0000 0000h 4.0 A1:A0 4010 0000h 0000 0000h 4.0
A3:A2 xxxx xxxxh xxxx xxxxh A3:A2 3FE0 0000h 0000 0000h 0.5
Pipeline