Texas Instruments TMS320C67X/C67X+ DSP Car Speaker User Manual


 
Pipeline Operation Overview
Pipeline4-8 SPRU733
Table 41. Operations Occurring During Pipeline Phases (Continued)
Stage
Instruction
Type
Completed
During This PhaseSymbolPhase
Execute 2 E2 For load instructions, the address is sent to memory.
For store instructions, the address and data are sent
to memory.
Single-cycle instructions that saturate results set the
SAT bit in the SCR if saturation occurs.
For multiply, 2-cycle DP, and DP compare instruc-
tions, results are written to a register file.
For DP compare and ADDDP/SUBDP instructions,
the upper 32 bits of the source are read.
For MPYDP instruction, the lower 32 bits of src1 and
the upper 32 bits of src2 are read.
For MPYI and MPYID instructions, the sources are
read.
For MPYSPDP instruction, the src1 and the upper
32 bits of src2 are read.
Multiply
2-cycle DP
DP compare
Execute 3 E3 Data memory accesses are performed. Any multiply
instruction that saturates results sets the SAT bit in
the CSR if saturation occurs.
For MPYDP instruction, the upper 32 bits of src1 and
the lower 32 bits of src2 are read.
For MPYI and MPYID instructions, the sources are
read.
Store
Execute 4 E4 For load instructions, data is brought to the CPU
boundary
For MPYI and MPYID instructions, the sources are
read.
For MPYDP instruction, the upper 32 bits of the
sources are read.
For MPYI and MPYID instructions, the sources are
read.
For 4-cycle instructions, results are written to a
register file.
For INTDP and MPYSP2DP instructions, the lower
32 bits of the result are written to a register file.
4-cycle
This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction
does not write an y results or have any pipeline operation after E1.