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Register File Cross Paths
CPU Data Paths and Control2-6 SPRU733
2.4 Register File Cross Paths
Each functional unit reads directly from and writes directly to the register file
within its own data path. That is, the .L1, .S1, .D1, and .M1 units write to register
file A and the .L2, .S2, .D2, and .M2 units write to register file B. The register
files are connected to the opposite-side register file’s functional units via the
1X and 2X cross paths. These cross paths allow functional units from one data
path to access a 32-bit operand from the opposite side register file. The 1X
cross path allows the functional units of data path A to read their source from
register file B, and the 2X cross path allows the functional units of data path
B to read their source from register file A.
On the C67x DSP, six of the eight functional units have access to the register
file on the opposite side, via a cross path. The .M1, .M2, .S1, and .S2 units’ src2
units are selectable between the cross path and the same side register file. In
the case of the .L1 and .L2, both src1 and src2 inputs are also selectable
between the cross path and the same-side register file.
Only two cross paths, 1X and 2X, exist in the C6000 architecture. Thus, the
limit is one source read from each data path’s opposite register file per cycle,
or a total of two cross path source reads per cycle. In the C67x DSP, only one
functional unit per data path, per execute packet, can get an operand from the
opposite register file.
2.5 Memory, Load, and Store Paths
The C67x DSP has two 32-bit paths for loading data from memory to the regis-
ter file: LD1 for register file A, and LD2 for register file B. The C67x DSP also
has a second 32-bit load path for both register files A and B. This allows the
LDDW instruction to simultaneously load two 32-bit values into register file A
and two 32-bit values into register file B. For side A, LD1a is the load path for
the 32 LSBs and LD1b is the load path for the 32 MSBs. For side B, LD2a is
the load path for the 32 LSBs and LD2b is the load path for the 32 MSBs. There
are also two 32-bit paths, ST1 and ST2, for storing register values to memory
from each register file.
On the C6000 architecture, some of the ports for long and doubleword oper-
ands are shared between functional units. This places a constraint on which
long or doubleword operations can be scheduled on a data path in the same
execute packet. See section 3.7.5.
Register File Cross Paths / Memory, Load, and Store Paths