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TMS320C67x DSP Features and Options
Introduction1-6 SPRU733
The VelociTI architecture of the C6000 platform of devices make them the first
off-the-shelf DSPs to use advanced VLIW to achieve high performance
through increased instruction-level parallelism. A traditional VLIW architecture
consists of multiple execution units running in parallel, performing multiple
instructions during a single clock cycle. Parallelism is the key to extremely high
performance, taking these DSPs well beyond the performance capabilities of
traditional superscalar designs. VelociTI is a highly deterministic architecture,
having few restrictions on how or when instructions are fetched, executed, or
stored. It is this architectural flexibility that is key to the breakthrough efficiency
levels of the TMS320C6000 Optimizing C compiler. VelociTI’s advanced
features include:
Instruction packing: reduced code size
All instructions can operate conditionally: flexibility of code
Variable-width instructions: flexibility of data types
Fully pipelined branches: zero-overhead branching.