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Pipeline Operation Overview
Pipeline4-10 SPRU733
Registers used by the instructions in E1 are shaded in Figure 4−7. The multi-
plexers used for the input operands to the functional units are also shaded in
the figure. The bold crosspaths are used by the MPY and SUBSP instructions.
Figure 4−7. Pipeline Phases Block Diagram
CMPLTSP
DP
PR
PW
PS
PG
3232323232323232
256
ABSSP
SUB
LDDW
MVK
CMPLTSP
ABSSP
B
ADDSP
SUBSP
SUB
ZERO
LDDW
LDDW
ABSSP CMPLTSPADDSP
MVLDDW
BMPYSPSUBSPLDDW
Register file A Register file B
Data 2Data 1 3232
3232
(byte addressable)
Internal data memory
Data address 2Data address 1
98
76543210
16 1616
16
Data memory interface control
DC
MPYSP ADDSPLDDWMPYSP
32
E1
.L1
ADDSP
.S1
ABSSP
.D1.M1
MPYSP
01354 26871012 11 91415 13
0123456789101112131415
.L2
SUBSP
.S2.D2
MPYSP
.M2
Fetch
Decode
Execute
ADDSP
SUBSP
ADDSP
ADDSP
SUBSP
MVK
ADDSP MPYSP CMPLTSP
ADDSP ABSSP
LDDW
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
ZERO