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Interrupt Detection and Processing
5.4.5 Actions Taken During RESET Interrupt Processing
A low signal on the RESET pin is the only requirement to process a reset. Once
RESET makes a high-to-low transition, the pipeline is flushed and CPU regis-
ters are returned to their reset values. GIE, NMIE, and the ISTB in the ISTP
are cleared. For the CPU state after reset, see section 126.96.36.199.
During CPU cycles 15 through 21 of Figure 5−5, the following reset proces-
sing actions occur:
Processing of subsequent nonreset interrupts is disabled because the
GIE and NMIE bits are cleared.
A branch to the address held in ISTP (the pointer to the ISFP for INT0) is
forced into the E1 phase of the pipeline during cycle 16.
During cycle 16, IACK is asserted and the proper INUMn signals are
asserted to indicate a reset is being processed.
IF0 is cleared during cycle 17.
Code that starts running after reset must explicitly enable the GIE bit, the
NMIE bit, and IER to allow interrupts to be processed.