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Interrupts5-4 SPRU733
5.1.1.2 Nonmaskable Interrupt (NMI)
NMI is the second-highest priority interrupt and is generally used to alert the
CPU of a serious hardware problem such as imminent power failure.
For NMI processing to occur, the nonmaskable interrupt enable (NMIE) bit in
the interrupt enable register must be set to 1. If NMIE is set to 1, the only condi-
tion that can prevent NMI processing is if the NMI occurs during the delay slots
of a branch (whether the branch is taken or not).
NMIE is cleared to 0 at reset to prevent interruption of the reset. It is cleared
at the occurrence of an NMI to prevent another NMI from being processed. You
cannot manually clear NMIE, but you can set NMIE to allow nested NMIs.
While NMI is cleared, all maskable interrupts (INT4−INT15) are disabled.
5.1.1.3 Maskable Interrupts (INT4−INT15)
The CPUs of the C6000™ DSPs have 12 interrupts that are maskable. These
have lower priority than the NMI and reset interrupts. These interrupts can be
associated with external devices, on-chip peripherals, software control, or not
be available.
Assuming that a maskable interrupt does not occur during the delay slots of
a branch (this includes conditional branches that do not complete execution
due to a false condition), the following conditions must be met to process a
maskable interrupt:
The global interrupt enable bit (GIE) bit in the control status register (CSR) is
set to1.
The NMIE bit in the interrupt enable register (IER) is set to1.
The corresponding interrupt enable (IE) bit in the IER is set to1.
The corresponding interrupt occurs, which sets the corresponding bit in
the interrupt flags register (IFR) to 1 and there are no higher priority
interrupt flag (IF) bits set in the IFR.