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Index-10 SPRU733
returning from interrupt servicing 5-15
REVISION ID bits 2-13
RMODE bits
in FADCR 2-24
in FMCR 2-31
RSQRDP instruction 3-201
RSQRSP instruction 3-203
S
SADD instruction 3-205
SAT bit 2-13
SAT instruction 3-208
saturate a 40-bit integer to a 32-bit integer
(SAT) 3-208
serial fetch packets 3-17
set a bit field (SET) 3-210
set an individual interrupt 5-14
SET instruction 3-210
setting interrupts 5-14
setting the nonreset interrupt flag 5-16
setting the RESET
interrupt flag 5-19
shift
arithmetic shift left (SHL) 3-213
arithmetic shift right (SHR) 3-215
logical shift right (SHRU) 3-217
shift left with saturation (SSHL) 3-232
shift left with saturation (SSHL) 3-232
SHL instruction 3-213
SHR instruction 3-215
SHRU instruction 3-217
single-cycle instructions
.D-unit instruction constraints 4-54
.L-unit instruction constraints 4-48
.S-unit instruction constraints 4-34
block diagram 4-16
pipeline operation 4-16
single-precision data format 3-9
SMPY instruction 3-219
SMPYH instruction 3-221
SMPYHL instruction 3-222
SMPYLH instruction 3-224
SPDP instruction 3-226
SPINT instruction 3-228
SPTRUNC instruction 3-230
square-root reciprocal approximation
double-precision floating-point (RSQRDP) 3-201
single-precision floating-point (RSQRSP) 3-203
SSHL instruction 3-232
SSUB instruction 3-234
STB instruction
5-bit unsigned constant offset or register
offset 3-236
15-bit unsigned constant offset 3-238
STH instruction
5-bit unsigned constant offset or register
offset 3-240
15-bit unsigned constant offset 3-243
store
byte
to memory with a 5-bit unsigned constant
offset or register offset (STB) 3-236
to memory with a 15-bit unsigned constant
offset (STB) 3-238
halfword
to memory with a 5-bit unsigned constant
offset or register offset (STH) 3-240
to memory with a 15-bit unsigned constant
offset (STH) 3-243
word
to memory with a 5-bit unsigned constant
offset or register offset (STW) 3-245
to memory with a 15-bit unsigned constant
offset (STW) 3-247
store instructions
.D-unit instruction constraints 4-53
block diagram 4-19
conflicts 3-22
pipeline operation 4-18
syntax for indirect addressing 3-32
using circular addressing 3-31
using linear addressing 3-30
store or load to the same memory location,
rules 4-19
store paths 2-6
STW instruction
5-bit unsigned constant offset or register
offset 3-245
15-bit unsigned constant offset 3-247
SUB instruction 3-249
SUB2 instruction 3-268
SUBAB instruction 3-253
SUBAH instruction 3-255
SUBAW instruction 3-256