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Pipeline Execution of Instruction Types
4-17PipelineSPRU733
4.2.2 16 y 16-Bit Multiply Instructions
The 16 × 16-bit multiply instructions use both the E1 and E2 phases of the
pipeline to complete their operations (see Table 4−4). Figure 4−10 shows the
fetch, decode, and execute phases of the pipeline that the multiply instructions
use.
Figure 4−11 shows the operations occurring in the pipeline for a multiply. In the
E1 phase, the operands are read and the multiply begins. In the E2 phase, the
multiply finishes, and the result is written to the destination register. Multiply
instructions have one delay slot.
Table 4−4. 16 16-Bit Multiply Instruction Execution
Pipeline Stage
E1 E2
Read src1
src2
Written dst
Unit in use
.M
Figure 4−10. Multiply Instruction Phases
PG PS PW PR DP DC E1 E2
1 delay slot
Figure 4−11.Multiply Instruction Execution Block Diagram
(data)
Operands
Register file
Write results
Functional
unit
.M
E1
E2