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Overview
Interrupts5-2 SPRU733
5.1 Overview
Typically, DSPs work in an environment that contains multiple external
asynchronous events. These events require tasks to be performed by the DSP
when they occur. An interrupt is an event that stops the current process in the
CPU so that the CPU can attend to the task needing completion because of
the event. These interrupt sources can be on chip or off chip, such as timers,
analog-to-digital converters, or other peripherals.
Servicing an interrupt involves saving the context of the current process, com-
pleting the interrupt task, restoring the registers and the process context, and
resuming the original process. There are eight registers that control servicing
interrupts.
An appropriate transition on an interrupt pin sets the pending status of the
interrupt within the interrupt flag register (IFR). If the interrupt is properly
enabled, the CPU begins processing the interrupt and redirecting program
flow to the interrupt service routine.
5.1.1 Types of Interrupts and Signals Used
There are three types of interrupts on the CPUs of the TMS320C6000™DSPs.
Reset
Maskable
Nonmaskable
These three types are differentiated by their priorities, as shown in Table 5−1.
The reset interrupt has the highest priority and corresponds to the RESET
signal.
The nonmaskable interrupt has the second highest priority and corresponds
to the NMI signal. The lowest priority interrupts are interrupts 4−15
corresponding to the INT4−INT15 signals. RESET
, NMI, and some of the
INT4−INT15 signals are mapped to pins on C6000 devices. Some of the
INT4−INT15 interrupt signals are used by internal peripherals and some may
be unavailable or can be used under software control. Check your device-
specific data manual to see your interrupt specifications.