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TMS320C67x DSP Features and Options
40-bit arithmetic options add extra precision for vocoders and other
computationally intensive applications
Saturation and normalization provide support for key arithmetic
Field manipulation and instruction extract, set, clear, and bit counting
support common operation found in control and data manipulation
The C67x devices include these additional features:
Hardware support for single-precision (32-bit) and double-precision
(64-bit) IEEE floating-point operations.
32 × 32-bit integer multiply with 32-bit or 64-bit result.
In addition to the features of the C67x device, the C67x+ device is enhanced
for code size improvement and floating-point performance. These additional
Execute packets can span fetch packets.
Register file size is increased to 64 registers (32 in each datapath).
Floating-point addition and subtraction capability in the .S unit.
Mixed-precision multiply instructions.
32-KByte instruction cache that supports execution from both on-chip
RAM and ROM as well as from external memory through a VBUSP-based
external memory interface (EMIF).
Unified memory controller features support for flat on-chip data RAM and
ROM organizations for zero wait-state accesses from both load store units
of the CPU. The memory controller supports different banking organiza-
tions for RAM and ROM arrays. The memory controller also supports
VBUSP interfaces (two master and one slave) for transfer of data from the
system peripherals to and from the CPU and internal memory. A VBUSP-
based DMA controller can interface to the CPU for programmable bulk
transfers through the VBUSP slave port.