Texas Instruments TMS320C67X/C67X+ DSP Car Speaker User Manual

Pipeline Execution of Instruction Types
Pipeline4-28 SPRU733
4.2.10 ADDDP/SUBDP Instructions
The ADDDP/SUBDP instructions use the E1 through E7 phases of the pipeline
to complete their operations (see Table 412). The lower 32 bits of the result
are written on E6, and the upper 32 bits of the result are written on E7. The
ADDDP/SUBDP instructions are executed on the .L unit. The functional unit
latency for ADDDP/SUBDP instructions is 2. The status is written to the
FADCR on E6. Figure 422 shows the fetch, decode, and execute phases of
the pipeline that the ADDDP/SUBDP instructions use.
Table 412. ADDDP/SUBDP Instruction Execution
Pipeline Stage
E1 E2 E3 E4 E5 E6 E7
Read src1_l
Written dst_l dst_h
Unit in use
.L or .S .L or .S
Figure 422. ADDDP/SUBDP Instruction Phases
PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7
6 delay slots