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Control Register File
CPU Data Paths and Control2-22 SPRU733
2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
The NMI return pointer register (NRP) contains the return pointer that directs
the CPU to the proper location to continue program execution after NMI
processing. A branch using the address in NRP (B NRP) in your interrupt
service routine returns to the program flow when NMI servicing is complete.
The NRP is shown in Figure 2−12.
The NRP contains the 32-bit address of the first execute packet in the program
flow that was not executed because of a nonmaskable interrupt. Although you
can write a value to NRP, any subsequent interrupt processing may overwrite
Figure 2−12. NMI Return Pointer Register (NRP)
Legend: R = Readable by the MVC instruction; W = Writeable by the MVC instruction; -x = value is indeterminate after reset
2.7.12 E1 Phase Program Counter (PCE1)
The E1 phase program counter (PCE1), shown in Figure 2−13, contains the
32-bit address of the fetch packet in the E1 pipeline phase.
Figure 2−13. E1 Phase Program Counter (PCE1)
Legend: R = Readable by the MVC instruction; -x = value is indeterminate after reset