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Control Register File Extensions
2-23CPU Data Paths and ControlSPRU733
2.8 Control Register File Extensions
The C67x DSP has three additional configuration registers to support floating-
point operations. The registers specify the desired floating-point rounding
mode for the .L and .M units. They also contain fields to warn if src1 and src2
are NaN or denormalized numbers, and if the result overflows, underflows, is
inexact, infinite, or invalid. There are also fields to warn if a divide by 0 was
performed, or if a compare was attempted with a NaN source. Table 2−13 lists
the additional registers used. The OVER, UNDER, INEX, INVAL, DENn,
NANn, INFO, UNORD and DIV0 bits within these registers will not be modified
by a conditional instruction whose condition is false.
Table 2−13. Control Register File Extensions
Acronym Register Name Section
FADCR Floating-point adder configuration register 2.8.1
FAUCR Floating-point auxiliary configuration register 2.8.2
FMCR
Floating-point multiplier configuration register 2.8.3
2.8.1 Floating-Point Adder Configuration Register (FADCR)
The floating-point adder configuration register (FADCR) contains fields that
specify underflow or overflow, the rounding mode, NaNs, denormalized
numbers, and inexact results for instructions that use the .L functional units.
FADCR has a set of fields specific to each of the .L units: .L2 uses bits 31−16
and .L1 uses bits 15−0. FADCR is shown in Figure 2−14 and described in
Table 2−14.
Note:
For the C67x+ DSP, the ADDSP, ADDDP, SUBSP, and SUBDP instructions
executing in the .S functional unit use the rounding mode from and set the
warning bits in FADCR. The warning bits in FADCR are the logical-OR of the
warnings produced on the .L functional unit and the warnings produced by
the ADDSP/ADDDP/SUBSP/SUBDP instructions on the .S functional unit
(but not other instructions executing on the .S functional unit).