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Pipeline Operation Overview
Table 4−1. Operations Occurring During Pipeline Phases
Stage Phase Symbol During This Phase
PG The address of the fetch packet is determined.
PS The address of the fetch packet is sent to the memory.
Program wait PW A program memory access is performed.
PR The fetch packet is at the CPU boundary.
Dispatch DP The next execute packet of the fetch packet is deter-
mined and sent to the appropriate functional unit to be
Decode DC Instructions are decoded in functional units.
Execute 1 E1 For all instruction types, the conditions for the
instructions are evaluated and operands are read.
For load and store instructions, address generation is
performed and address modifications are written to the
For branch instructions, branch fetch packet in PG
phase is affected.
For single-cycle instructions, results are written to a
For DP compare, ADDDP/SUBDP, and MPYDP
instructions, the lower 32-bits of the sources are read.
For all other instructions, the sources are read.
For MPYSPDP instruction, the src1 and the lower
32 bits of src2 are read.
For 2-cycle DP instructions, the lower 32 bits of the
result are written to a register file.
This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction
does not write an y results or have any pipeline operation after E1.